1. Technical Field
The present invention relates to a power-off circuit.
2. Related Art
Referring to FIG. 4, a power-off circuit in related art is shown. A power management unit 20 is electrically connected between an integrated circuit chip (IC chip, e.g., CPU) 40 and a power unit 10 which supplies power, and used for controlling power supplied via power lines 61 and 62 to the IC chip 40. A switching apparatus 30 is connected to the power management unit 20 and used to supply instructions including a power-off instruction to the power management unit 20 at a user's operation. The power management unit 20 includes a detection unit 21 and a control unit 22. The detection unit 21 detects the power off instruction supplied by the switching apparatus 30 and accordingly transmits a power-off notice to the IC chip 40 via a signal line 52. The IC chip 40 includes a reset circuit 41 and a control circuit 42. The control circuit 42 affirms the power off notice and feeds back a power-off affirmation to the power management unit 20 via a signal line 53. The control unit 22 of the power management unit 20 then cuts off the power supplied to the IC chip 40.
According to the power-off circuit in the related art, if the user transiently operates the switching apparatus 30 and decreases the power supplied to the IC chip 40, the reset circuit 41 of the IC chip 40 finds that the power supply thereto is decreased and produces a reset signal to the power management unit 20 via the signal line 53. The reset signal causes the control unit 22 of the power management unit 20 to resume the power supply of the IC chip 40. Therefore, a transient operation on the switching apparatus 30 hardly powers off the IC chip 40.
Therefore, there is a need for providing a power-off circuit which can solve the above-mentioned problem.